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1. A ripple counter is a (n):

(A) Synchronous Counter (B) Asynchronous counter

(C) Parallel counter (D) None of the above

Answer: B

Explanation:

A ripple counter is an asynchronous counter where only the first flip-flop is clocked by an external clock. All subsequent flip-flops are clocked by the output of the preceding flip-flop. Asynchronous counters are also called ripple-counters because of the way the clock pulse ripples it way through the flip-flops.

The MOD of the ripple counter or asynchronous counter is 2ⁿ if n flip-flops are used. For a 4-bit counter, the range of the count is 0000 to 1111 (2⁴-1). A counter may count up or count down or count up and down depending on the input control. The count sequence usually repeats itself. When counting up, the count sequence goes from 0000, 0001, 0010, … 1110 , 1111 , 0000, 0001, … etc. When counting down the count sequence goes in the opposite manner: 1111, 1110, … 0010, 0001, 0000, 1111, 1110, … etc.

The complement of the count sequence counts in reverse direction. If the uncomplemented output counts up, the complemented output counts down. If the uncomplemented output counts down, the complemented output counts up.

There are many ways to implement the ripple counter depending on the characteristics of the flip flops used and the requirements of the count sequence.

• Clock Trigger: Positive edged or Negative edged
• JK or D flip-flops
• Count Direction: Up, Down, or Up/Down

Asynchronous counters are slower than synchronous counters because of the delay in the transmission of the pulses from flip-flop to flip-flop. With a synchronous circuit, all the bits in the count change synchronously with the assertion of the clock. Examples of synchronous counters are the Ring and Johnson counter.

2. 8085 microprocessor has …………… bit ALU.

(A) 32 (B) 16

(C) 8 (D) 4

Answer: C

Explanation:

The Intel 8080, 8085, and Zilog Z80 are considered 8 bits, because that was the size of their accumulators and most of their registers, although it’s program counter was 16 bits, and specific pairs of registers could be combined to form 16 bit values or addresses.

The Intel 8086 and 8088 are considered a 16 bits, but the 8086 accesses memory 16 bits at a time, while the otherwise identical 8088 accesses memory 8 bits at a time. It had 20 bits for addressing memory (so it could support up to 1 MB). The main registers are 16 bits wide, but some of them can be accessed 8 bits at at time (AX can be accessed as AH (high order part) or AL (low order part)).

The Intel 80386 is a 32 bit cpu. The 80386 normally accesses memory 32 bits at a time with a 32 bit addresses. Motorola 68000 16/32 bit processor has 32 bit regisers, but accesses memory 16 bits at a time with a 24 bit address. The Motorola 68020 accessed memory 32 bits at a time. The Intel Pentium Pro is also a 32 bit cpu, but some versions had 36 bits of addressing, that required using address translation schemes. For a typical PC, the amount of memory that can be read at one time varies with the motherboard and cpu, normally it’s 64 bits (called double channel) or 96 bits (called triple channel).

3. The register that stores the bits required to mask the interrupts is …………….

(A) Status register (B) Interrupt service register

(C) Interrupt mask register (D) Interrupt request register

Answer: C

Explanation: Interrupt Mask Register operates on IRR(Interrupt Request Register) at the direction of the Priority Resolver.

4. Which of the following in 8085 microprocessor performs

HL = HL + HL ?

(A) DAD D (B) DAD H

(C) DAD B (D) DAD SP

Answer: B

Explanation:

HL= HL+ HL means DAD H

5. In …………… addressing mode, the operands are stored in the memory. The address of the corresponding memory location is given in a register which is specified in the instruction.

(A) Register direct (B) Register indirect

(C) Base indexed (D) Displacement

Answer: B

Explanation:

The different types of instructions are as follows:

– Immediate Mode: As the name suggests the instruction in itself contains the operand.

– Register Mode: In this mode the operands of an instruction are placed in the registers which themselves are placed inside the CPU.

– Direct address mode: The address part of an instruction in this mode is the effective address.

– Indexed addressing mode: In this mode in order to obtain the effective address the contents of the index register is added to the instructions address part.

– Relative address mode: In this mode in order to find out the effective address the contents of the program counter are added to the address part of the instruction.

-Register Indirect Addressing: Register indirect addressing is similar to indirect addressing, except that the address field refers to a register instead of a memory location. It requires only one memory reference and no special calculation.

6. The output of the following combinational circuit is :

(A) X . Y (B) X + Y

(C) X xor Y (D) X xnor Y

Answer: D

Explanation:

It gives the output same as XNOR.

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7. Which of the following statements is/are True regarding some advantages that an object-oriented DBMS (OODBMS) offers over a relational database? I .An OODBMS avoids the “impedance mismatch” problem. II. An OODBMS avoids the “phantom” problem. III. An OODBMS provides higher performance concurrency control than most relational databases. IV. An OODBMS provides faster access to individual data objects once they have been read from disk.

(A) II and III only (B) I and IV only

(C) I, II, and III only (D) I, III and IV only

Answer: B

Explanation:

only B option correct as advantages of OODBMS

8. The Global conceptual Schema in a distributed database contains information about global relations. The condition that all the data of the global relation must be mapped into the fragments, that is, it must not happen that a data item which belongs to a global relation does not belong to any fragment, is called :

(A) Disjointness condition (B) Completeness condition

(C) Reconstruction condition (D) Aggregation condition

Answer: B

Explanation:

Completeness condition is the answer because above question is definition of it.

9. Suppose database table T1(P, R) currently has tuples {(10, 5), (15, 8), (25, 6)} and table T2 (A, C) currently has {(10, 6), (25, 3), (10, 5)}. Consider the following three relational algebra queries RA1, RA2 and RA3:

The number of tuples in the resulting table of RA1, RA2 and RA3 are given by:

(A) 2, 4, 2 respectively (B) 2, 3, 2 respectively

(C) 3, 3, 1 respectively (D) 3, 4, 1 respectively

Answer: D

10. Consider the table R with attributes A, B and C. The functional dependencies that hold on R are : A → B, C → AB. Which of the following statements is/are True? I. The decomposition of R into R1(C, A) and R2(A, B) is lossless. II. The decomposition of R into R1(A, B) and R2(B, C) is lossy.

(A) Only I (B) Only II

(C) Both I and II (D) Neither I nor II

Answer: C

Explanation:

1.R1(C,A) R1(A,B)

R1∩R2 =A which is super key for A

so its lossless join .

2.R1(A,B) R1(B,C)

R1∩R2=B which is not super key for any relation so its lossy join .

both are correct

11. Consider the following ORACLE relations:

One (x, y) = {<2, 5>, <1, 6>, <1, 6>, <1, 6>, <4, 8>, <4, 8>}

Two (x, y) = {<2, 55>, <1, 1>, <4, 4>, <1, 6>, <4, 8>, <4, 8>, <9, 9>, <1, 6>}

Consider the following two SQL queries SQ1 and SQ2:

SQ1 : SELECT * FROM One)

EXCEPT

(SELECT * FROM Two);

SQ2 : SELECT * FROM One)

EXCEPT ALL

(SELECT * FROM Two);

For each of the SQL queries, what is the cardinality (number of rows) of the result obtained when applied to the instances above?

(A) 2 and 1 respectively (B) 1 and 2 respectively

(C) 2 and 2 respectively (D) 1 and 1 respectively

Answer: B

Explanation;

EXCEPT returns distinct rows from the left input query that aren’t output by the right input query.

The EXCEPT ALL operator does not remove duplicates. For purposes of row elimination and duplicate removal, the EXCEPT operator does not distinguish between NULLs.

12. Which one of the following pairs is correctly matched in the context of database design?

List – I List – II

(Database term) (Definition)

1. Specialization A. Result of taking the union of two or more

disjoint (lower-level) entity sets to produce

a higher-level entity set. 2. Generalization B. Express the number of entities to which another

entity can be associated via a relationship set.

3. Aggregation C. Result of taking a subset of a higher-level

entity set to form a lower-level entity set. 4. Mapping cardinalities D. An abstraction in which relationship sets (along

with their associated entity sets) are treated as

higher-level entity sets, and can participate in

relationships.

Codes :

I II III IV

(A) D A B C

(B) D C B A

(C) C D A B

(D) C A D B

Answer: D

Explanation:

Specialization: It uses Top to bottom approach means higher to lower

Generalizion: it uses bottom to up approach means lower to high.

Aggregation: it is treated as higher-level entity sets and can participate in relationships.

Mapping cardinalities: number of entities to which another entity can be associated via a relationship set.

13. Consider a raster grid having XY-axes in positive X-direction and positive upward Y-direction with X_max = 10, X_min = –5, Y_max = 11, and Y_min = 6. What is the address of memory pixel with location (5, 4) in raster grid assuming base address 1 (one)?

(A) 150 (B) 151

(C) 160 (D) 161

Answer: D

14. Consider a N-bit plane frame buffer with W-bit wide lookup table with W > N. How many intensity levels are available at a time?

(A) 2^N (B) 2^W

(C) 2^N+W (D) 2^N–1

Answer: A

Explanation:

A frame buffer is a large, contiguous piece of computer memory. At a minimum there is one memory bit for each pixel in the rater; this amount of memory is called a bit plane. The picture is built up in the frame buffer one bit at a time.

N-bit colour Frame buffer:

Color or gray scales are incorporated into a frame buffer rater graphics device by using additional bit planes. The intensity of each pixel on the CRT is controlled by a corresponding pixel location in each of the N bit planes. The binary value from each of the N bit planes is loaded into corresponding positions in a register. The resulting binary number is interpreted as an intensity level between 0 (dark) and 2ⁿ -1 (full intensity).

This is converted into an analog voltage between 0 and the maximum voltage of the electron gun by the DAC. A total of 2^N intensity levels are possible. Figure given below illustrates a system with 3 bit planes for a total of 8 (2³) intensity levels. Each bit plane requires the full complement of memory for a given raster resolution; e.g., a 3-bit plane frame buffer for a 1024 X1024 raster requires 3,145,728 (3 X 1024 X1024) memory bits.

15. Consider the Breshenham’s line generation algorithm for a line with gradient greater than one, current point (x_i, y_i) and decision parameter, d_i. The next point to be plotted (x_i+1, y_i+1) and updated decision parameter, d_i+1, for d_i < 0 are given as ……………..

(A) x_i+1 = x_i+1

y_i+1 = y_i

d_i+1 = d_i + 2 dy

(B) x_i+1 = x_i

y_i+1 = y_i + 1

d_i+1 = d_i + 2 dx

(C) x_i+1 = x_i

y_i+1 = y_i + 1

d_i+1 = d_i + 2 (dx – dy)

(D) x_i+1 = x_i + 1

y_i+1 = y_i + 1

d_i+1 = d_i + 2 (dy – dx)

Answer: B

Explanation;

According to Breshenham’s line generation algorithm , the formula of above question is

x_i+1 = x_i

y_i+1 = y_i + 1

d_i+1 = d_i + 2 dx

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